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nand flash-based solid state disk 1 sep. 27. 2006 module type product data sheet version 1.1 sep 2006 (nand flash-based solid state disk) * samsung electronics reserves the right to c hange products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for use in life su pport, critical care, medical, safety equipment, or sim- ilar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procuremen t to which special terms or provisions may apply. n s s d
nand flash-based solid state disk 2 sep. 27. 2006 document title samsung nand flash-base d solid state disk revision history the attached data sheets are prepared and approved by sams ung electronics. and samsung electronics has the right to change all the specifications in data sheet s. samsung electronics will evaluate and reply to any dear customer?s requests and questions on the parameters of this devic e. if dear customer has any questions, pleas e call or fax to memory product planning team, or contact the samsung branch office near your office revision no 0.5 1.0 1.1 history initial issue physical dimension was added(slim 4/8/16gb) gnd pad was added on slim 32gb supporting security feature set supporting smart feature set supporting host protected area feature set identify device data was updated software/hardware reset state diagram was added misprint was modified(page 56) ( in graph, r/b -> bsy) product line-up was added(page 65) (a-die based small 8/16gb) (shared pcb based slim 4/8/16/32gb) draft date may.09.2006 aug.18.2006 sep.27.2006 remark preliminary final final
nand flash-based solid state disk 3 sep. 27. 2006 table of contents 1. general description 2. physical specifications 2.1 small type ph ysical dim ensions(16gb) 2.2 slim type physical dimensions ( 4/8/16gb) 2.3 slim type phys ical dimensions(32gb) 3. product specifications 3.1 system interface and configuration 3.2 system performance 3.3 system power consumption 3.4 system reliability 3.5 environmental specifications 4. electrical specifications 4.1 zif connector dimensions 4.2 pin assignment 4.3 signal descriptions 4.4 dc characteristics 4.4.1 absolute maximum ratings 4.4.2 recommended operating conditions 4.4.3 electrical characteristics 4.5 ac characteristics 4.5.1 register transfers 4.5.2 pio data transfers 4.5.3 multiword dma data transfer 4.5.3.1 initiating a multiword dma data burst 4.5.3.2 sustaining a multiword dma data burst 4.5.3.3 device terminating a multiword dma data burst 4.5.3.4 host terminating a multiword dma data burst 4.5.4 ultra dma data transfer 4.5.4.1 initiating an ultra dma data-in burst 4.5.4.2 sustained ultra dma data-in burst 4.5.4.3 host pausing an ultra dma data-in burst 4.5.4.4 device terminating an ultra dma data-in burst 4.5.4.5 host terminating an ultra dma data-in burst 4.5.4.6 initiating an ultra dma data-out burst 4.5.4.7 sustained ultra dma data-out burst 4.5.4.8 device pausing an ultra dma data-out burst 4.5.4.9 host terminating an ultra dma data-out burst 4.5.4.10 device terminating an ultra dma data-out burst 5. ata registers 5.1 i/o register descriptions 5.2 alternate status register 5.2.1 address 5.2.2 direction 5.2.3 access restrictions 5.2.4. effect 5.2.5 functional description 5.3 command register 5.3.1 address 5.3.2 direction 5.3.3 access restrictions 5.3.4 effect 5.3.5 functional description 5.3.6 field/bit description 5.4 cylinder high register 5.4.1 address 5.4.2 direction 5.4.3 access restrictions 5.4.4 effect 6 7 7 9 11 13 13 13 13 13 13 14 14 14 15 16 16 16 16 17 17 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 37 37 37 37 37 37 37 38 38 38 38 38 38 38 39 39 39 39 39
nand flash-based solid state disk 4 sep. 27. 2006 table of contents 5.4.5 functional description 5.5 cylinder low register 5.5.1 address 5.5.2 direction 5.5.3 access restrictions 5.5.4 effect 5.5.5 functional description 5.6 data port 5.6.1 address 5.6.2 direction 5.6.3 access restrictions 5.6.4 effect 5.6.5 functional description 5.6.6 field/bit description 5.7 data register 5.7.1 address 5.7.2 direction 5.7.3 access restrictions 5.7.4 effect 5.7.5 functional description 5.7.6 field/bit description 5.8 device control register 5.8.1 address 5.8.2 direction 5.8.3 access restrictions 5.8.4 effect 5.8.5 functional description 5.8.6 field/bit description 5.9 device/head register 5.9.1 address 5.9.2 direction 5.9.3 access restrictions 5.9.4 effect 5.9.5 functional description 5.9.6 field/bit description 5.10 error register 5.10.1 address 5.10.2 direction 5.10.3 access restrictions 5.10.4 effect 5.10.5 functional description 5.10.6 field/bit description 5.11 features register 5.11.1 address 5.11.2 direction 5.11.3 access restrictions 5.11.4 effect 5.11.5 functional description 5.12 sector count register 5.12.1 address 5.12.2 direction 5.12.3 access restrictions 5.12.4 effect 5.12.5 functional description 5.13 sector number register 5.13.1 address 5.13.2 direction 5.13.3 access restrictions 5.13.4 effect 5.13.5 functional description 5.14 status register 39 40 40 40 40 40 40 40 40 40 41 41 41 41 42 42 42 42 42 42 42 43 43 43 43 43 43 43 44 44 44 44 44 44 44 45 45 45 45 45 45 45 46 46 46 46 46 46 47 47 47 47 47 47 48 48 48 48 48 48 49
nand flash-based solid state disk 5 sep. 27. 2006 table of contents 5.14.1 address 5.14.2 direction 5.14.3 access restrictions 5.14.4 effect 5.14.5 functional description 5.14.6 field/bit description 5.14.6.1 bsy(busy) 5.14.6.2 drdy(device ready) 5.14.6.3 command dependent 5.14.6.4 drq(data request) 5.14.6.5 obsolete bits 5.14.6.6 err(error) 6. command descriptions 6.1 supporting ata command set 6.2 security feature set 6.2.1 securtity mode default setting 6.2.2 initial setting of the user password 6.2.3 security mode operation from power-on 6.2.4 password lost 6.3 smart feature set 6.3.1 sub command set 6.3.2 smart data structure(read data(doh)) 6.3.3 threshold sector size 6.4 r/b status in sleep command 6.5 set features 6.5.1 set features register value 6.6 set max 6.6.1 set max features register value 6.7 identify device data 6.8 hardware reset state diagram 6.9 software reset state diagram 7. ordering information 8. product line-up 49 49 49 49 49 49 50 51 51 51 51 52 53 53 54 54 54 54 54 55 55 55 56 56 57 57 58 58 59 61 62 64 65
nand flash-based solid state disk 6 sep. 27. 2006 fifo & control ecc ecc fifo & control the nssd(nand flash-based solid state disk) of samsung electronics is fu lly consist of semiconduc tor device and using nand flash memory which has a hi gh reliability and a high technology for a storage media. as the nssd doesn't have a moving parts su ch as platter(disk) and head media, it gi ves a good solution in a sub. note pc and ta blet pc for a storage device with a high performance and a power consumption and a small form factor. also it gives rugged features in industrial pc with an extreme environment and an increased mtbf. for an easy adoption, the nssd has a same host interface with hdd and has a same physical dimension. ? density ? 8 gb,16gb,32gb nssd are available ? form factor ? small type (56 x 48 x 3.8mm) : 8/16gb ? slim type (53.60 x 70.60 x 3.00mm) :32gb (53.60 x 70.60 x 2.50mm) : 4/8/16gb ? host interface ? pio mode 0 to 4. ? multiword dma ? up to ata5 udma mode4 (66mhz) ? performance ? host interface : max 66mb/s ? sustained data read : max 56mb/s ? sustained data write : max 32mb/s ? power consumption ? active : typical 200ma ? idle : typical 20ma ? standby : typical 20ma ? temperature ? operating : -25'c ~ 85'c ? shock ? operating : 1500g, duration 0.5ms, half sine wave ? vibration : 20g peak, 10~2000h z,(12cycle/axis)x3 axis ? mtbf ? 1,000,000 hours host sram controller voltage detector & power on reset initial fsm p-ata udma host conf_reg arm7 flash conf_reg arm i/f flash memory controller sram control & data path flash memory controller flash memory ? x8 x32 x32 x16 x8 x32 x16 x16 x8 x8 x16 x32 1. general description ? nssd functional block diagram flash memory flash memory flash memory flash memory flash memory x8 x8 flash memory x16 flash memory flash memory flash memory flash memory flash memory x8 x8
nand flash-based solid state disk 7 sep. 27. 2006 2.1 small type physical dimensions (8/16gb) 2. physical specifications 3.53 0.61 56 3.66 0.61 5.5 8.5 5.5 5.5 48 figure 1. small type(8/16gb) top 2.5 2.5 3.0 2.0 1.05 nand nand controller 176 lqfp r 0.5
nand flash-based solid state disk 8 sep. 27. 2006 15.65 9.28 9.99 22.00 18.35 figure 2. small type(8/16gb) bottom 3.01 nand nand nand nand nand nand 1.75 3.5 connector contact no. 1 r 0.5 figure 3. small type(8/16gb) side connector nand 1.20 3.8 0.3 0.8 1.8 capacitor pcb nand
nand flash-based solid state disk 9 sep. 27. 2006 53.60 2.0 6.4 0.5 0.5 17.15 22.00 14.45 1.35 70.60 figure 4. slim type(4/8/16gb) top 2.2 slim type physical dimensions (4/8/16gb) contact no. 1 nand nand nand nand nand nand nand nand controller 180fbga r 0.5 connector 2.5 2.5 4.01 5.20 0.5 1.05
nand flash-based solid state disk 10 sep. 27. 2006 53.60 figure 5. slim type(4/8/16) bottom 70.60 r 0.5 figure 6. slim type(4/8/16gb) side ic chip nand 2.50 0.15 0.68 1.20 pcb nand 5.5 5.5 5.5 5.5 5.5 2.5 3.0 8.5 2.0 1.05 1.75
nand flash-based solid state disk 11 sep. 27. 2006 53.60 2.0 6.4 0.5 0.5 17.15 22.00 14.45 1.35 70.60 figure 7. slim type(32gb) top 2.3 slim type physical dimensions (32gb) contact no. 1 nand nand nand nand nand nand nand nand controller 180fbga r 0.5 connector 2.5 2.5 4.01 5.20 0.5 1.05
nand flash-based solid state disk 12 sep. 27. 2006 53.60 figure 8. slim type(32gb) bottom 70.60 r 0.5 figure 9. slim type(32gb) side nand 2.35 pcb nand 5.5 5.5 5.5 5.5 5.5 2.5 3.0 8.5 2.0 1.05 connector 3.00 0.15 0.68
nand flash-based solid state disk 13 sep. 27. 2006 (sandra 2005, 32gb) read / write performance(mb/s) random read sector max 56 random write sector max 13 sequential read sector max 56 sequential write sector max 32 (32gb) current typical(ma) active 200 idle 20 standby 20 ? pio 0~4 mode, ? up to ata5 and udma mode4(ultra dma66) ? fully compatible with ata5 specification mtbf 1,000,000 hours 3.1 system interface and configuration 3.2 system performance 3.4 system reliability 3.3 system power consumption 3. product specifications features operating non-operating temperature -25?c ~ 85?c -40?c ~ 85?c humidity 0?c to 55?c / 90~98% rh, 10cycles vibration 20g peak, 10 ~ 2000hz, (12cycle / axis) x3 axis shock 1500g, duration 0.5ms, half sine wave 3.5 environmental specifications
nand flash-based solid state disk 14 sep. 27. 2006 4.1 zif connector dimensions 4.2 pin assignment pin no signals pin no signals 1reserved 21 ground 2reserved 22 dmarq 3 reset 23 ground 4 ground 24 diow 5dd7 25 dior 6dd8 26 ground 7dd6 27 iordy 8dd9 28 ground 9dd5 29 dmack 10 dd10 30 intrq 11 dd4 31 da1 12 dd11 32 pdiag 13 dd3 33 da0 14 dd12 34 da2 15 dd2 35 cs0 16 dd13 36 cs1 17 dd1 37 dasp 18 dd14 38 3.3v 19 dd0 39 3.3v 20 dd15 40 reserved 0.5 0.10 19.50 22.00 4.00 2.07 1.17 4.93 0.9 0.10 contact no. 1 figure 7. connector top figure 8. connector side *zif: zero insertion force 4. electrical specification
nand flash-based solid state disk 15 sep. 27. 2006 signal name pin no type description reset 3i this is a reset signal output from t he host system and to be used for inter- face logic circuit. dd0 - dd15 5-20 i/o this is a 16bit bi-directional data bus. the lover 8 bits are used for register acess other that data register. diow 24 i this rising edge of this write str obe signal clocks data from the host data bus into a register on the device. stop* assertion of this signal by the hos t during an ultra dma burst signals the termination of the ultra dma burst. dior 25 i activating this read strobe signal enabl es data from a register on the device to be clocked onto the host data bus. the rising edge of this signal latches data at the host. hdmardy* this signal is a flow control signal for ultra dma read. host asserts this signal, and indicates that the host is ready to receive ultra dma read data. hstrobe* this signal is write data strobe signal from the host for an ultra dma write. both the rising and falling edge latch the data from dd(15:0) into the device. iordy 27 o this signal is used to temporarily stop the host register access(read or write) when the device is not ready to respond to a data transfer request. ddmardy* this signal is flow control signal for ultra dma write. device asserts this signal, and indicates that the device is ready to receive ultra dma write data. dstrobe* this signal is the data in strobe signal from the device for an ultra dma read. both the rising and falling edge latch the data from dd(15:0) into the host. intrq 30 o this is an interrupt signal for the host system. this signal is asserted by a selected device when the nien bit in the device control register is "0". in other cases, this signal should be a high impedance state. da0-2 31,33,34 i this is a register address signal from the host system. pdiag :cblid* 32 i/o the host shall wait until the power on or hardware reset sequence is com- plete for all devices on the cable; cs0 35 i this device chip selection signal is used to select the control block regis- ters from the host system. cs1 36 i this device chip selection signal is used to select the command block registers from the host system. dasp 37 i/o this signal indicates that a device is active when the power is turned on. upon receipt of a command from the host, the device asserts this signal. at command completion, the device de-asserts this signal. dmarq 22 o the device shall assert this signal , used for dma data transfers between host and device, when it is ready to transfer data. dmack 29 i the host in response to dmarq to ei ther acknowledge that data has been accepted, or that data is av ailable shall use this signal. devadr 40 i the device is configured as either de vice 0(master) or device 1(slave) depending upon the signal level of 40 pin devadr signal. - when used as device 1(master), devadr is open - when used as device 1(slave), the host shall have pull-up resistor. rec- ommended pull-up register is 10k ohm based on +3.3vcc. "i" of i/o type represents an input signal from the dev ice and "o" represents an output signal from the device. 4.3 signal descriptions
nand flash-based solid state disk 16 sep. 27. 2006 4.4.1 absolute maximum ratings characteristics symbol rating unit dc supply voltage v dd -0.3 to 4.6 v input/output voltage v in /v out 3.8 v dc input current i in +/- 200 ma storage temperature t stg -40 to 85 c 4.4.2 recommended operating conditions characteristics symbol rating unit dc supply voltage v dd 3.0 to 3.6 v input/output voltage v in /v out 3.0 to 3.6 v operating temperature t opr -25 to 85 c 4.4.3 electrical characteristics - normal i/o vdd = 3.0 to 3.6(v), ta = 25( c), vext = 5v 0.25v note : * schmitt trigger test condition : v dd = 3.0 to 3.6(v), ta = 25( c) characteristic : these dc parameters guarantee the i/o cell characteristic at the static state only, not at the dynamic state. characteristics symbol test condition min typ max unit input high current i ih v in = v dd pull - down normal down -10 10 - - 10 60 ua ua input low current i il v in = v ss pull - up normal up -10 -60 - - 10 -10 ua ua input high voltage v ih cmos 2.0 - - v input low voltage v il cmos - - 0.8 v output high voltage v oh 6ma buffer, i oh = -6ma 2.4 - - v output low voltage v ol 6ma buffer, i ol = 6ma - - 0.4 v tri-state output leakage current i oz v out = v dd or v ss -10 - 10 ua 4.4 dc characteristics
nand flash-based solid state disk 17 sep. 27. 2006 figure 1 defines the relationships betwe en the interface signals for register trans fers. peripherals reporting support for pio mode 3 or 4 shall power-up in a pio mode 0,1, or 2. for pio modes 3 and above, the minimum value of t 0 is specified by word 68 in the iden tify device parameter list. table 1 defines the minimum value that shall be placed in word 68. both hosts and devices shall support iordy when pio mo de 3 or 4 are the currently selected mode of operation. dior-/diow- write dd(7:0) read dd(7:0) iordy t 1 addr valid t 2 (see note 1) (see note 2) (see note 2) (see note 3,3-2) iordy (see note 3,3-1) iordy (see note 3,3-3) t 9 t 0 t 3 t 4 t 5 t 6 t 6z t a t c t rd t b t c note: 1. device address consists of signals cs0-, cs1- and da(2:0) 2. data consists of dd(7:0) 3. the negation of iordy by the device is used to extend the register transfer cycle. the determination of whether the cycle is to be extended is made by the host after t a from the assertion of dior- or diow-. the assertion and negation of iordy are described in the following three cases: 3-1. device never negates iordy, devices keeps iordy released: no wait is generated. 3-2. device negates iordy before t a , but causes iordy to be asserted before t a . iordy is released prior to negation and may be asserted for no more than 5ns before release: no wait generated. 3-3. device negates iordy before t a . iordy is released prior to negation and may be asserted for no more than 5ns before release: wait generated. the cycle completes after iordy is reasserted. for cycles where a wait is generat ed and dior- is asserted, the device shall place read data on dd(7:0) for t rd before asserting iordy. 4. dmack- shall remain negated during a register transfer. figure 1. register transfer to/from device. t 2i 4.5.1 register transfers 4.5 ac characteristics
nand flash-based solid state disk 18 sep. 27. 2006 table 1 - register transfer to/from device note : 1. t 0 is the minimum total cycle time, t 2 is the minimum dior-/diow- assertion time, and a host implementation shall lengthen t 2 and/or t 2i to ensure that t 0 is equal to or greater than the value reported in the devices indentify device data. a device implementation shall support any legal host implementation. 2. this parameter specifies the time from the negation edge of dior- to the time that the data bus is released by the device. 3. the delay from the activation of dior- or diow- until the stat e of iordy is first sampled. if iordy is inactive then the hos t shall wait until iordy negated at the t a after the activation of dior- or diow-, then t 5 shall be met and t rd is not applicable. if the device is driving iordy negated at the time t a after the activation of dior- or diow-, then t rd shall be met and t 5 is not applicable. 4. ata/atapi standards prior to ata/atapi- 5 inadvertently specified an incorrect value for mode2 time t0 by utilizing the 16-bi t pio value. 5. mode shall be selected no faster than the highest mode supported by the slowest device. register transfer timing parameters mode 0ns mode 1ns mode 2ns mode 3ns mode 4ns note t 0 cycle time min 600 383 330 180 120 1,4,5 t 1 address valid to dior-/diow- setup min 70 50 30 30 25 t 2 dior-/diow- pulse width 8bit min 290 290 290 80 70 1 t 2i dior-/diow- recovery time min - - - 70 25 1 t 3 diow- data setup min 60 45 30 30 20 t 4 diow- data hold min 30 20 15 10 10 t 5 dior- data setup min 50 35 20 20 20 t 6 dior- data hold min 5 5 5 5 5 t 6z dior- data tristate max 30 30 30 30 30 2 t 9 dior-/diow- to address valid hold min 20 15 10 10 10 t rd read data valid to iordy active (if iordy initially low after t a ) min0 0 000 t a iordy setup time 35 35 35 35 35 3 t b iordy pulse width max 1250 1250 1250 1250 1250 t c iordy assertion to release max 5 5 5 5 5
nand flash-based solid state disk 19 sep. 27. 2006 figure 2 defines the relationships between the interface signals for pio data transfers. peripherals reporting support for pio mode 3 or 4 shall power-up in a pio mode 0,1, or 2. for pio modes 3 and above, the minimum value of t 0 is specified by word 68 in the identify device parameter list. table 2 defines the minimum value that shall be placed in word 68. iordy shall be supported when pio mode 3 or 4 are the current mode of operation. dior-/diow- write dd(15:0) iordy t 1 addr valid t 2 (see note 1) (see note 2) (see note 3,3-2) iordy (see note 3,3-1) iordy (see note 3,3-3) t 9 t 0 t 3 t 4 t 5 t 6 t 6z t a t c t rd t b t c note: 1. device address consists of signals cs0-, cs1- and da(2:0) 2. data consists of dd(15:0) for all devic es except devices implementing the cfa feat ure set when 8-bit transfers is enabled. i n that case, data consists of dd(7:0) 3. the negation of iordy by th e device is used to extend the pio cycle. the determination of whether the cycle is to be extende d is made by the host after t a from the assertion of dior- or diow-. the assertion and negation of iordy are described in the following three cases: 3-1. device never negates iordy, devices keeps iordy released: no wait is generated. 3-2. device negates iordy before t a , but causes iordy to be asserted before t a . iordy is released prior to negation and may be asserted for no more than 5ns before release: no wait generated. 3-3. device negates iordy before t a . iordy is released prior to negation and may be asserted for no more than 5ns before release: wait generated. the cycle completes after iordy is reasserted. for cycles where a wait is generat ed and dior- is asserted, the device shall place read data on dd(7:0) for t rd before asserting iordy. 4. dmack- shall be negated during a pio data transfer. figure 2. pio data transfer to/from device. dd(7:0) t 2i read dd(15:0) (see note 2) dd(7:0) 4.5.2 pio data transfers
nand flash-based solid state disk 20 sep. 27. 2006 table 2 - pio data transfer to/from device note : 1. t 0 is the minimum total cycle time, t 2 is the minimum dior-/diow- assertion time, and t 21 is the minimum dior-/diow- negation time. a host imple- mentation shall lengthen t 2 and/or t 2i to ensure that t 0 is equal to or greater than the value reported in the devices identify device data. a device implementation shall support any legal host implementation. 2. this parameter specifies the time from the negation edge of dior- to the time that the data bus is released by the device. 3. the delay from the activation of dior- or diow- until the stat e of iordy is first sampled. if iordy is inactive then the hos t shall wait until iordy is active before the pio cycle is completed. if th e device is not drivi ng iordy negated at the t a after the activation of dior- or diow-, then t 5 shall be met and t rd is not applicable. if the device is driving iordy negated at the time t a after the activation of dior- or diow-, then t rd shall be met and t 5 is not applicable. 4. mode may be selected at the highest mode for the device if cs(1:0) and ad(2:0) do not change between read or write cycles or selected at the high- est mode supported by the slowest device if cs(1:0) or ad(2:0) do change between read or write cycles. pio timing parameters mode 0ns mode 1ns mode 2ns mode 3ns mode 4ns note t 0 cycle time min 600 383 240 180 120 1,4 t 1 a d d r e s s v a l i d t o d i o r - / d i o w- s e t u p m i n 7 0 5 0 3 0 3 0 2 5 t 2 dior-/diow- min 165 125 100 80 70 1 t 2i dior-/diow- recovery time min - - - 70 25 1 t 3 diow- data setup min 60 45 30 30 20 t 4 diow- data hold min 30 20 15 10 10 t 5 dior- data setup min 50 35 20 20 20 t 6 dior- data hold min 5 5 5 5 5 t 6z dior- data tristate max 30 30 30 30 30 2 t 9 dior-/diow- to address valid hold min 20 15 10 10 10 t rd read data valid to iordy active (if iordy initially low after t a ) min0 0 000 t a iordy setup time 35 35 35 35 35 3 t b iordy pulse width max 1250 1250 1250 1250 1250 t c iordy assertion to release max 5 5 5 5 5
nand flash-based solid state disk 21 sep. 27. 2006 figure 3 through figure 6 define the timing associated with multiword dma transfers. for multiword dma modes 1 and above, the minimum value of t 0 is specified by word 65 in the identify device parameter list. table 3 defines the minimum value that shall be placed in word 65. devices shall power-up with mode 0 as the default multiword dma mode. table 3 - multiword dma data transfer note : > t 0 is the minimum total cycle time, t d is the minimum dior-/diow- assertion time, and t k (t kr or t kw , as appropriate) is the minimum dior-/diow- negation time. a host shall lengthen t d and/or t k to ensure that t 0 is equal to the value reported in the devices identify device data. multiword dma timing parameters mode 0ns mode 1ns mode 2ns note t 0 cycle time min 480 150 120 see note t d dior-/diow- asserted pulse width min 215 80 70 see note t e dior- data access max 150 60 50 t f dior- data hold min 5 5 5 t g dior-/diow-data setup min 100 30 20 t h diow- data hold min 20 15 10 t i dmack to dior-/diow- data setup min 0 0 0 t j dior-/diow- to dmack hold min 20 5 5 t kr dior- negated pulse width min 50 50 25 see note t kw diow- negated pulse width min 215 50 25 see note t lr dior- to dmarq delay max 120 40 35 t lw diow- to dmarq delay max 40 40 35 t m cs(1:0) valid to dior-/diow- min 50 30 25 t n cs(1:0) hold min 15 10 10 t z dmack- to read data released max 20 25 25 4.5.3 multiword dma data transfers
nand flash-based solid state disk 22 sep. 27. 2006 the values for the timings for each of the multiword dma modes are contained in table 50. dmarq write cs0-/cs1- dd(15:0) read dd(15:0) t m figure 3. initiating a multiword dma data transfer dior-/diow- dmack- see note see note t e t d t g t g t f t h note: the host shall not assert dmack- or negate both cs0 and cs1 until th e assertion of dmarq is detected. the maxium time from the assertion of dmarq to the assertion of dmack- or the negation of both cs0 and cs1 is not defined. 4.5.3.1 initiating a multiword dma data burst
nand flash-based solid state disk 23 sep. 27. 2006 the values for the timings for each of the multiword dma modes are contained in table 50. dmarq write cs0-/cs1- dd(15:0) read dd(15:0) figure 4. sustaining a multiword dma data transfer dior-/diow- dmack- t d t 0 t k t e t g t f t e t g t f t g t h t g t h 4.5.3.2 sustaining a multiword dma data burst
nand flash-based solid state disk 24 sep. 27. 2006 the values for the timings for each of the multiword dma modes are contained in table 50. dmarq write cs0-/cs1- dd(15:0) read dd(15:0) figure 5. device terminating a multiword dma data transfer dior-/diow- dmack- t 0 t k t e t g t f t g t h (see note) t n t l t d t j t z note: to terminate the data burst, the host shall negate dmarq within the tl of the assertion of the current dior- or diow- pulse. th e last data word for the burst shall then be transferred by the negation of the current dior- or diow- pulse. if all data for the command has not been t ransferred, the host shall reassert dmarq again at any later time to resume the dma operation. 4.5.3.3 device terminating a multiword dma data burst
nand flash-based solid state disk 25 sep. 27. 2006 the values for the timings for each of the multiword dma modes are contained in table 50. dmarq write cs0-/cs1- dd(15:0) read dd(15:0) figure 6. host terminating a multiword dma data transfer dior-/diow- dmack- t 0 t k t e t g t f t g t h (see note 2) t n t d t j t z note: 1. to terminate the transmission of a data burst, the host shall negate dmack- within the specified time after a dior- or diow- pulse. no further dior- or diow- pulses shall be asserted for this burst. 2. if the device is able to continue the transfer of data, the host may leave dmarq asserted and wait for the host to reassert dmack- or may negate dmarq at any time after detecting that dmack- has been negated. (see note 1) 4.5.3.4 host terminating a multiword dma data burst
nand flash-based solid state disk 26 sep. 27. 2006 figure 7 through figure 16 define the timings as sociated with all phases of ultra dma bursts. table 4 contains the values for the ti mings for each of the ultra dma modes. table 4 - ultra dma data burst timing requirements note : 1. timing parameters shall be measured at th e connector of the sender or receiver to which the parameter applies. for example, the sender shall stop generating strobe edges t rfs after the negation of dmardy-. both strobe and dmardy- timing measurements are taken at the connector of the sender. 2. all timing measurement switching points(low to high and high to low) shall be taken at 1.5v. 3. t ui , t mli , and tli indicate sender-to-recipient or recipient-to-sender interlocks, i. e., either sender or recipient is waiting for the other to r espond with a signal before proceeding. t ui is an inlimited interlock that has no maximum time value. t mli is a limited time-out that has a defined minimum. t li is a lim- ited time-out that has a defined maximum. 4. the test load for t dvs and t dvh shall be a lumped capacitor load with no cable or receivers. timing for t dvs and t dvh shall be met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value. 5. t ziordy may be greater than t env since the device has a pull up on iordy- giving it a known state when released. name mode 0 mode 1 mode 2 mode 3 mode 4 comment (see notes 1 and 2) min max min max min max min max min max t 2cyctyp 240 160 120 90 60 typical sustained average two cycle time t cyc 11273543925 cycle time allowing for asymmetry and clock varia- tions (from strobe edge to strobe edge) t 2cyc 230 154 115 86 57 two cycle time allowing for clock variations (from ris- ing edge to next rising edge or from falling edge to next falling edge of strobe) t ds 15 10 7 7 5 data setup time at recipient t dh 5 5 5 5 5 data hold time at recipient t dvs 70 48 30 20 6 data valid setup time at sender (from data valid until strobe edge) (see note 4) t dvh 66666 data valid hold time at sender (from strobe edge until data may become invalid) (see note 4) t fs 0 230 0 200 0 170 0 130 0 120 first strobe time (for device to first negate dstrobe from stop during a data in burst) t li 0 150 0 150 0 150 0 100 0 100 limited interlock time (see note 3) t mli 20 20 20 20 20 interlock time with minimum(see note 3) t ui 0 0 0 0 0 unlimited interlock time (see note 3) t az 10 10 10 10 10 maximum time allowed for output drivers to release (from asserted or negated) t zah 20 20 20 20 20 minimum delay time required for output t zad 0 0 0 0 0 drivers to assert or negate (from released) t env 20 70 20 70 20 70 20 55 20 55 envelope time (from dmack- to stop and hdmardy- during data in burst initiation and from dmack to stop during data out burst initiation) t sr 50 30 20 na na strobe-to-dmardy- time (if dmardy- is negated before this long after strobe edge, the recipient shall receive no more than one additional data word) t rfs 75 70 60 60 60 ready-to-final-strobe time (no strobe edges shall be sent this long after negation of dmardy-) t rp 160 125 100 100 100 minimum time to assert stop or negate dmarq t iordyz 20 20 20 20 20 maximum time before releasing iordy t ziordy 0 0 0 0 0 minimum time before driving strobe (see note 5) t ack 20 20 20 20 20 setup and hold times for dmack- (before assertion or negation) t ss 50 50 50 50 50 time from strobe edge to negation of dmarq or assertion of stop (when sender terminates a burst) 4.5.4 ultra dma data burst
nand flash-based solid state disk 27 sep. 27. 2006 the values for the timings for each of the ultra dma modes are contained in 4.4.4 dmack- dmarq dd(15:0) dstrobe (device) figure 7. initiating an ultra dma data-in burst hdmardy- stop (host) t ui (host) (device) (host) da0,da1,da2, cs0-,cs1- t ack t env t fs t zad t ack t env t zad t fs t ziordy t az t dvs t dvh t ack note: 1. the definitions for the diow-:stop, dior -:hdmardy-:hstrobe and iordy:ddmardy-:dstrobe signal lines are not in effect until d marq and dmack are asserted. 4.5.4.1 initiating an ultra dma data-in burst
nand flash-based solid state disk 28 sep. 27. 2006 the values for the timings for each of the ultra dma modes are contained in 4.4.4 dd(15:0) dstrobe figure 8. sustained ultra dma data-in burst at device t cyc at device t cyc dstrobe at host dd(15:0) at host t 2cyc t 2cyc t dvh t dvs t dvh t dvs t dvh t dh t dh t ds t dh t ds note: 1. dd(15:0) and dstrobe signals are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at th e host until some time after they are driven by the device. 4.5.4.2 sustained ultra dma data-in burst
nand flash-based solid state disk 29 sep. 27. 2006 the values for the timings for each of the ultra dma modes are contained in 4.4.4 dmack- dmarq dd(15:0) dstrobe (device) figure 9. host pausing an ultra dma data-in burst hdmardy- stop (host) (host) (device) (host) t sr t rfs note: 1. the host mat assert stop to request termination of the ultra dma burst no sooner than trp after hdmardy- is negated. 2. if the t sr timing is not satisfied, the host may receive zero, one, or two more data words from the host. (device) t rp 4.5.4.3 host pausing an ultra dma data-in burst
nand flash-based solid state disk 30 sep. 27. 2006 the values for the timings for each of the ultra dma modes are contained in 4.4.4 dmack- dmarq crc dstrobe (device) hdmardy- stop (host) (host) (device) (host) da0,da1,da2, cs0-,cs1- t ss t mli t ack t li t li t li t az t zah t ack t iordyz t ack t dvh dd(15:0) figure 10. device terminating an ultra dma data-in burst note: 1. the definitions for the diow-:stop, dior-:hdmardy-:hstrobe and iordy:ddmardy-:dstrobe signal lines are no longer in effect a fter dmarq and dmack are negated. 4.5.4.4 device terminating an ultra dma data-in burst
nand flash-based solid state disk 31 sep. 27. 2006 the values for the timings for each of the ultra dma modes are contained in 4.4.4 dmack- dmarq dstrobe (device) hdmardy- stop (host) (host) (device) (host) da0,da1,da2, cs0-,cs1- t rfs t mli t ack t rp t zah t ack t iordyz t ack t dvh dd(15:0) figure 11. host terminating an ultra dma data-in burst note: 1. the definitions for the diow-:stop, dior-:hdmardy-:hstrobe and iordy:ddmardy-:dstrobe signal lines are no longer in effect a fter dmarq and dmack are negated. t li t az t li t mli t dvs 4.5.4.5 host terminating an ultra dma data-in burst crc
nand flash-based solid state disk 32 sep. 27. 2006 the values for the timings for each of the ultra dma modes are contained in 4.4.4 dmack- dmarq dstrobe (device) hdmardy- stop (host) (host) (device) (host) da0,da1,da2, cs0-,cs1- t ack t dvh dd(15:0) figure 12. initiating an ultra dma data-out burst note: 1. the definitions for the diow-:stop,iordy:ddmardy-:dstrobe and dior-:hdmardy-:hstrobe signal lines are no longer in effect af ter dmarq and dmack are negated. t dvs t ui t env t ziordy t li t ack t ui t ack 4.5.4.6 initiating an ultra dma data-out burst
nand flash-based solid state disk 33 sep. 27. 2006 the values for the timings for each of the ultra dma modes are contained in 4.4.4 note: 1. dd(15:0) and hstrobe signals are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host. dd(15:0) hstrobe figure 13. sustained ultra dma data-out burst at host t cyc at host t cyc hstrobe at device dd(15:0) at device t 2cyc t 2cyc t dvh t dvs t dvh t dvs t dvh t dh t dh t ds t dh t ds 4.5.4.7 sustained ultra dma data-out burst
nand flash-based solid state disk 34 sep. 27. 2006 the values for the timings for each of the ultra dma modes are contained in 4.4.4 figure 14. device pausing an ultra dma data-out burst note: 1. the device may negate dmarq to request termination of the ultra dma burst no sooner that t rp after ddmardy- is negated. 2. if the t sr timing is not satisfied, the device may receive zero,one,or two more data words from the host. stop dmack- dd(15:0) hstrobe (host) ddmardy- dmarq (host) (device) (host) (device) t sr t rfs (host) t rp 4.5.4.8 device pausing an ultra dma data-out burst
nand flash-based solid state disk 35 sep. 27. 2006 the values for the timings for each of the ultra dma modes are contained in 4.4.4 dmack- dmarq crc dstrobe (device) hdmardy- stop (host) (host) (device) (host) da0,da1,da2, cs0-,cs1- t ss t mli t ack t li t li t ack t iordyz t ack t dvh dd(15:0) figure 15. host terminating an ultra dma data-out burst note: 1. the definitions for the diow-:stop,iordy:ddmardy-:dstrobe and dior-:hdmardy-:hstrobe signal lines are no longer in effect af ter dmarq and dmack are negated. t li t dvs (host) 4.5.4.9 host terminating an ultra dma data-out burst
nand flash-based solid state disk 36 sep. 27. 2006 the values for the timings for each of the ultra dma modes are contained in 4.4.4 dmack- dmarq crc hstrobe (host) ddmardy- stop (host) (host) (device) (device) da0,da1,da2, cs0-,cs1- t rfs t mli t rp t ack t dvh figure 16. device terminating an ultra dma data-out burst note: 1. the definitions for the diow-:stop,iordy:ddmardy-:dstrobe and dior-:hdmardy-:hstrobe signal lines are no longer in effect af ter dmarq and dmack are negated. t li t li t mli t dvs dd(15:0) (host) t ack t iordyz t ack 4.5.4.10 device terminating an ultra dma data-out burst
nand flash-based solid state disk 37 sep. 27. 2006 5.1 i/o register descriptions communication to or from the device is th rough registers addressed by the signals from the host(cs0-,cs1-, da(2:0), dior-, and diow), cs0- and cs1- both asserted or negated is an invalid (not used) address except when both are negated during a dma data transfer. when cs0- and cs1- are both asserted or both negated and a dma transfer is not in progress, the device shall hold dd (15:0) in the released state and ignore transitions on dior- and di ow-. when cs0- is negated and cs1- is asserted only da (2:0) with a value of 6th is valid. during invali d combinations of assertion and negation of cs0-, cs1-, da0, da1, and da2, a device shall keep dd(15:0) in the high impedance state and ignore transitions on dior- and diow-. valid register addresses are described in the clauses defining the registers. address - the cs and da address of the register. direction - indicates if the register is read/write, read only, or write only from the host. access restrictions - indicates when the register may be accessed. effect - indicates the effect of accessing the register. functional description - describes the function of the register. field/bit description - describes the content of the register. 5.2 alternate status register 5.2.1 address cs1 cs0 da2 da1 da0 ana a n a=asserted, n=negated 5.2.2 direction 5.2.3 access restrictions 5.2.4. effect 5.2.5 functional description this register is read only. if this address is written to by the host, the device control register is written. when the bsy bit is set to one, the other bits in this register shall not be used. the entire contents of this register are not valid while the device is in sleep mode. reading this register shall not clear a pending interrupt. this register contains the sa me information as the status register in the command block. 5. ata registers
nand flash-based solid state disk 38 sep. 27. 2006 5.3 command register 5.3.1 address cs1 cs0 da2 da1 da0 naa a n a=asserted, n=negated this register is write only. if this address is read by the host, the status register is read. 5.3.3 access restrictions for all commands, this register shall only be written when bsy and drq are both cleared to zero and dmack- is not asserted. if written when bsy or drq is set to one, the results of writing the command register are indeterminate. 5.3.4 effect 5.3.5 functional description 5.3.6 field/bit description 7 6 5 4 3 2 1 0 command code command prcessing begins when this register is writte. the content of the command bl cok registers become parameters of the command when this register is written. writing this register clears any pending interrupt condition. this register contains the command code being sent to the device . command execution begins immediat ely after this register is w rit- ten. 5.3.2 direction
nand flash-based solid state disk 39 sep. 27. 2006 5.4.4 effect the content of this register becomes a command parameter when the comand register is written. 5.4.5 functional description the content of this register is command dependent 5.4.3 access restrictions this register shall be written only when both bsy and drq are cleared to zero and dmack- is noet asserted. the contents of this register are valid only when bsy is cleared to zero. if this register is written when bsy or drq is set to one, the result is indeterminate. the contents of this regist er are not valid while a device is in the sleep mode. 5.4.2 direction this register is read/write. 5.4 cylinder high register 5.4.1 address cs1 cs0 da2 da1 da0 naa n a a=asserted, n=negated
nand flash-based solid state disk 40 sep. 27. 2006 5.5.1 address cs1 cs0 da2 da1 da0 naa n n a=asserted, n=negated 5.5.2 direction 5.5.4 effect 5.5.3 access restrictions this register is read/write. this register shall be written only when both bsy and dr q are cleared to zero and dmack- is not asserted. the contents of this register are valid only when bsy is cleared to zero. if this register is written when bsy or drq is set to one, the result is indeterminate. the contents of this regist er are not valid while a device is in the sleep mode. the content of this register becomes a command parameter when the command register is written. 5.6 data port cs1 cs0 da2 da1 da0 nnx x x a=asserted, n=negated, x=don?t care 5.5.5 functional description the content of this register is command dependent 5.6.1 address when dmack- is asserted, cs0- and cs1- shal l be negated and transfers shall be 16-bits wide. 5.6.2 direction this register is read/write. 5.5 cylinder low register
nand flash-based solid state disk 41 sep. 27. 2006 5.6.3 access restrictions this port shall be accessed for host dma data transfers only when dmack- and dmarq are asserted. 5.6.4 effect the content of this register becomes a command parameter when t he command register is written. dma out data transfers are pro- cessed by a series of reads to this port, each read transferring the data that follows the previous read. dma in data transfers are pro- cessed by a series of writes to this por t, each write transferring the data that follows the previous write. the results of a r ead during a dma in or a write during a dma out are indeterminate. the data port is 16-bits in width. 5.6.6 field / bit description 15 14 13 12 11 10 9 8 data(15:8) 76 5 43 2 10 data(7:0) 5.6.5 functional description
nand flash-based solid state disk 42 sep. 27. 2006 5.7 data register 5.7.1 address cs1 cs0 da2 da1 da0 nan n n a=asserted, n=negated 5.7.2 direction this register is read/write. 5.7.3 access restrictions this register shall be accessed for host pio data transfer only when drq is set to on and dmack- is not asserted. the contents of this register are not valid while a device is in the sleep mode. 5.7.4 effect pio out data transfers are processed by a series of reads to th is register, each read transferring the data that follows the pr evious read. pio in data transfers are processed by a series of writes to this register, each write transferring the data that follows the previ- ous write. the results of a read during a pio in or a write during a pio out are indeterminate. 5.7.5 functional description the data port is 16-bits in width. when a cfa device is in 8-bi t pio data transfer mode this regi ster is 8-bits wide using only dd7 to dd0. 5.7.6 field / bit description 15 14 13 12 11 10 9 8 data(15:8) 76543 2 10 data(7:0)
nand flash-based solid state disk 43 sep. 27. 2006 5.8.1 address cs1 cs0 da2 da1 da0 ana a n a=asserted, n=negated 5.8.6 field / bit description ? bits 7 through 3 are reserved. ? srst is the host software reset bit. ? nien is the enable bit for the device asse rtion of intrq to the host. when the nien bit is cleared to zero, and the device is selected, intrq shall be enabled through a tri-state buffer and shal l be asserted or negated by the device as appropriate. whe n the nien bit is set to one, or the device is not selected, the intrq signal shall be in a high impedance state. ? bit 0 shall be cleared to zero. 76 5 43 2 10 rr r rrsrstnien0 5.8.2 direction this register is write only. if th is address is read by the host, the alternate status register is read. 5.8.3 access restrictions this register shall only be written when dmack- is not asserted. 5.8.4 effect the content of this register shall take effect when written. 5.8.5 functional description this register allows a host to software reset attached devices and to enable or disable the assertion of the intrq signal by a selected device. when the device control register is written, both devices respond to the write regardless of which device is selected. when the srst bit is set to one, both devices shall perform the software reset protocol. the device shall respond to the srst bit when in the sleep mode. 5.8 device control register
nand flash-based solid state disk 44 sep. 27. 2006 5.9.1 address cs1 cs0 da2 da1 da0 naa a n a=asserted, n=negated note: some hosts set these bits to one. devices shall ignore these bits. ? obsolete:these bits are obsolete. ? #:the content of these bits is command dependent ? dev: device select. cleared to zero selects device 0. set to one selects device1. 7 6 5 43210 obsolete # obsolete dev # # # # 5.9.2 direction this register is read/write. 5.9.3 access restrictions this register shall be written only when both bsy and drq are cleared to zero and dmack- is not asserted. the contents of this register are valid onl y when bsy is cleared to zero. if this register is written when bsy or drq is set to one, the result is indeterminate. 5.9.4 effect the dev bit becomes effective when this regi ster is written by the host or the signatur e is set by the device. all other bits i n this reg- ister become a command parameter when the command register is written. 5.9.5 functional description but 4, dev, in this register selects the device . other bits in this register are command dependent. 5.9.6 field / bit description the content of this register shall take effect when written. 5.9 device / head register
nand flash-based solid state disk 45 sep. 27. 2006 5.10.1 address cs1 cs0 da2 da1 da0 nan n a a=asserted, n=negated 5.10.6 field / bit description ? bit 2: abrt(command aborted) is set to one to indicate the requested command has been command aborted because the com- mand code or a command parameter is invalid or some other error has occurred. ? #: the content of this bit is command dependent 76543210 #####abrt## 5.10.2 direction this register is read only. if this address is written to by the host, the features register is written. 5.10.3 access restrictions the contents of this register shall be valid when bsy and drq equal zero and err equals one. the contents of this register shall be valid upon completion of power-on, or after a hardware or software reset, or after comma nd completion of an execute device diagnostics. the contents of th is register are not valid while a devcie is in the sleep mode. 5.10.4 effect none. 5.10.5 functional description this register contains status for the current command. following a power-on, a hardware or software reset, or command completion of an execute device diagnostic, this register contains a diagnostic code. at command description of any command except execute device diagnostic, the contents of this register are valid when the err bit is set to one in the status register. 5.10 error register
nand flash-based solid state disk 46 sep. 27. 2006 5.11.1 address cs1 cs0 da2 da1 da0 nan n a a=asserted, n=negated 5.11.2 direction this register is write only. if this address is read by the host, the error register is read. 5.11.3 access restrictions this register shall be written only when bsy and drq equal zero and dmack- is not asse rted. if this register is written when bs y or drq is set to one, the result is indeterminate. 5.11.4 effect the content of this register becomes a command parameter when the command register is written. 5.11.5 functional description the content of this register is command dependent. 5.11 features register
nand flash-based solid state disk 47 sep. 27. 2006 5.12 sector count register 5.12.1 address cs1 cs0 da2 da1 da0 nan a n a=asserted, n=negated 5.12.2 direction this register is read/write. 5.12.3 access restrictions this register shall be written only when bsy and drq equal zero and dmack- is not asserted. the contents of this register are v alid only when both bsy and drq are zero. if this register is written wh en bsy or drq is set to one, the result is indeterminate. th e con- tents of the this register are not va lid while a device is in the sleep mode. 5.12.4 effect the content of this register becomes a command parameter when the command register is written. 5.12.5 functional description the content of this register is command dependent.
nand flash-based solid state disk 48 sep. 27. 2006 5.13.1 address cs1 cs0 da2 da1 da0 nan a a a=asserted, n=negated 5.13.2 direction this register is read/write. 5.13.3 access restrictions this register shall be written only when bsy and drq equal zero and dmack- is not asserted. the contents of this register are v alid only when both bsy and drq are zero. if this register is written wh en bsy or drq is set to one, the result is indeterminate. th e con- tents of the this register are not va lid while a device is in the sleep mode. 5.13.4 effect the content of this register becomes a command parameter when the command register is written. 5.13.5 functional description the content of this register is command dependent. 5.13 sector number register
nand flash-based solid state disk 49 sep. 27. 2006 5.14 status register 5.14.1 address cs1 cs0 da2 da1 da0 naa a a a=asserted, n=negated 5.14.2 direction this register is read only. if this address is written to by the host, the command register is written. 5.14.3 access restrictions the contents of this register, except for bsy, shall be ignored wh en bsy is set to one. bsy is valid at all times. the contents of this register are not valid while a device is in the sleep mode. 5.14.4 effect reading this register when an interrupt is pending causes the interrupt pending to be cleared. the host should not read the st atus register when an interrupt is expected as this may clear t he interrupt pending before the intrq can be recognized by the host. 5.14.6 field / bit description 76543210 bsy drdy # # drq obsolete obsolete err the register contains the device status. th e contents of this register are updated to reflect the current state of the device a nd the progress of any command bei ng executed by the device. 5.14.5 functional description
nand flash-based solid state disk 50 sep. 27. 2006 5.14.6.1 bsy(busy) bsy is set to one to indicate that device is busy. after the host has written the command regist er the device shall have either the bsy bit set to one, or the drq bit set to one, until command comp letion or the device has performed a bus release for an overla pped command. the bsy bit shall be set to one by the device : 1) after either the negation of reset- or the setting of the srst bit to one in the device control regitster; 2) after writing the command register if the drq bit is not set to one; 3) between blocks of a data transfer during pio data- in commands before the drq bit is cleared to zero; 4) after the transfer of a data block during pio data- out commands before the drq bit is cleared to zero; 5) during the data transfer of dma commands either the bsy bit, the drq bit, or both shall be set to one; note: the bsy bit may be set to one and then cleared to zero so quickly, that host detection of the bsy bit being set to one is not c ertain. when bsy is set to one, the device has control of the command block registers and; 1) a write to a command block register by the host shal l be ignored by the device except for writing device reset command; 2) a read from a command block register by the host will most likely yield invalid contents except for the bsy bit itself. the bsy bit shall be cleared to zero by the device: 1)after setting drq to one to indicate is ready to transfer data; 2) at command completion; 3) upon releasing the bus for an overlapped command; 4) when the device is ready to accept commands that do not require drdy during a power on, hardware or software reset. when bsy is cleared to zero, the host has control of the command block registers, the device shall: 1) not set drq to one; 2) not change err bit; 3) not change the content of any other command block register; 4) set the serv bit to one when ready to cont inue an overlapped command that has been bus released.
nand flash-based solid state disk 51 sep. 27. 2006 the drdy bit shall be set to one by the device : 1) when the device is capable of accepting all commands for devices when the drdy bit is set to one : 1) the device shall accept and attempt to execute all implemented commands; 2) devices that implement the power management feature set shall maintain the drdy bit set to one when they are in the idle or standby modes. 5.14.6.3 command dependent the use of bits marked with # are command dependent. bit 4 was formerly the dsc(device seek complete) bit. 5.14.6.4 drq(data request) drq indicates that the device is ready to transfer a word of data between the host and the device. after the host has written t he command register the device shall either set the bsy bit to one or the drq bit to one, until command completion or the device h as performed a bus release for an overlapped command. the drq bit shall be set to one by the device : 1) when bsy is set to one and data is ready for pio transfer; 2) during the data transfer of dma commands either the bsy bit, the drq bit, or both shall be set to one. when the drq bit is set to one, the host may : 1) transfer data via pio mode; 2) transfer data via dma mode if dmarq and dmack- are asserted. the drq bit shall be cleared to zero, the host may : 1) transfer data via dma mode if dmarq and dmack- are asserted and bsy is set to one. 5.14.6.5 obsolete bits some bits in this register were defined in previous ata standards but have been declared obsolete in this spec these bits are labeled "obsolete". 5.14.6.2 drdy(device ready)
nand flash-based solid state disk 52 sep. 27. 2006 err indicates that an error occurred duri ng execution of the previous command. the err bit shall be set to one by the device : 1) when bsy or drq is set to one and an error occurs in the executing command. when the err bit is set to one : 1) the bits in the error register shall be valid; 2) the device shall not change the contents of the following r egisters until a new command has been accepted, the srst bit is s et to one or reset- is asserted : ? error register ? cylinder high/low register ? sector count register ? sector number register ? device / head register the err bit shall be cleared to zero by the device : 1) when a new command is written to the command register; 2) when the srst bit is set to one; 3) when the reset- signal is asserted. when the err bit is cleared to zero at the end of a command: 1) the content of the error register shall be ignored by the host. 5.14.6.6 err(error)
nand flash-based solid state disk 53 sep. 27. 2006 *1 : refer to 6.3.1 *2 : refer to 6.5.1 *3 : refer to 6.6.1 command name command code command name command code recalibrate 10h idle e3h read sector(s) 20h read buffer e4h write sector(s) 30h check power mode e5h read verify sector(s) 40h sleep e6h seek 70h flush cache e7h execute device diagno stic 90h write buffer e8h initialize device parameters 91h identify device ech smart *1 b0h set features *2 efh read multiple c4h security set password f1h write multiple c5h security unlock f2h set multiple mode c6h security erase prepare f3h read dma c8h security erase unit f4h write dma cah security freeze lock f5h standby immediate e0h security disable password f6h idle immediate e1h read native max address f8h stanby e2h set max *3 f9h 6. command descriptions 6.1 supporting ata command set
nand flash-based solid state disk 54 sep. 27. 2006 the security mode features allow the host to implement a securt ity password system to prevent unauthorized access to the disk drive. the nssd is shipped with master password set to 2 0h value(ascii blanks) and the lock function disabled. the system manufacturer/dealer may set a new master pa ssword by using the security set password command, without enableing the lock function. when a user password is set, the drive automatic ally enters lock mode by the next powered-on in locked mode, the nssd rejects media access commands until a security unlock command is successfully completed. if the user password is lost and high level security is set, the drive does not allow the user to access any data. however, the drive can be unlo cked using the master password. if the user password is lost and maxium security level is set, it is impossible to access data. however, the drive can be unlocked using the erase unit command with the master password. the drive will erase all user data and unlock the drive. the execution time of security erase unit command is shown below. - 32gb nssd : 60 seconds - 16gb nssd : 30 seconds 6.2 security feature set 6.2.1 security mode default setting 6.2.2 initial setting of the user password 6.2.3 security mode operation from power-on 6.2.4 password lost
nand flash-based solid state disk 55 sep. 27. 2006 smart read data d0h read log d5h read attribute thresholds d1h enable operations d8h enable/disable autosave d2h disable operations d9h save attribute values d3h return status dah execute off-line immidiate d4h change threshold sector size e0h byte f/v descriptions 0~1 x revision code 2~3 x valid information count 4~7 v total number of sectors for replacement 8~11 v number of sectors actually replaced 12~15 x number of sectors initially mapped out 16~19 v threshold sector size [default value :19000h(50mb)] 19~361 x vendor specific 362 v off-line data collection status 363 x self-test execution status byte 364~365 v total time in seconds to comp lete off-line data collection activity 366 x vendor specific 367 f off-line data collection capability 368-369 f smart capability 370 f error logging capability 7-1 reserved 0 1=device error logging supported 371 x vendor specific 372 f short self-test routine re commended polling time(in minutes) 373 f extended self-test routine recommended polling time(in minutes) 374-385 r reserved 386-510 x vendor specific 511 v data structure checksum key : f=the content of the byte is fixed and does not change. v=the content of the byte is variable and may change depending on the state of the device or the commands executed by the device. x=the content of the byte is vendor specific and may be fixed or variable. r=the content of the byte is reserved and shall be zero. 6.3 smart feature set 6.3.2 smart data structure(read data(d0h)) 6.3.1 sub command set
nand flash-based solid state disk 56 sep. 27. 2006 threshold sector size is an predefined value that makes the wari ng message if the number of reserved sector size is below this value. the status can be read from cylinder register by read data(d0h) command. deafult value of the cylinder register has c24fh, but if the num ber of reserved sector size is below the treshold sector size, the cylinder register has 2cf4h. in order to change the threshold sector size, should be set the changed value in sector count register with change thresh- old sector size (e0h) command. sector count register value (unit : mb, range : 0~199) in sleep command, nssd takes 1ms to get into sleep state. during this period, all the command operation is prohibitted. the status register value is d0h after getting into sleep state. sleep command issue sleep command clear wait 1 msec nssd is set to sleep state bsy 6.3.3 threshold sector size 6.4 bsy status in sleep command
nand flash-based solid state disk 57 sep. 27. 2006 default settings after power on are data transfer mode of ultra dma mode 4, pio mode 4 and write cache enabled. set features enable write cache 02h set transfer mode 03h disable write cache 82h 6.5 set features 6.5.1 set features register value
nand flash-based solid state disk 58 sep. 27. 2006 each of set max commands is identified by the value placed in the feature register. below table shows these features register values. set max set max address 01h set max set password 02h set max lock 03h set max freeze lock 04h set max unlock 05h 6.6 set max 6.6.1 set max features register value
nand flash-based solid state disk 59 sep. 27. 2006 word 16gb 32gb description 0 0x0040 0x0040 general information 1 0x3fff 0x3fff number of logical cylinders 2 0x0000 0x0000 specific configuration 3 0x0010 0x0010 number of logical heads 4 - 5 0x0000 0x0000 retired 6 0x003f 0x003f number of logical sectors per logical track 7 - 8 0x0000 0x0000 reserved 9 0x0000 0x0000 retired 10 -19 0xxxxx 0xxxxx serial number(20 ascii characters) 20 - 21 0x0000 0x0000 retired 22 0x0000 0x0000 obsolete 23 - 26 0xxxxx 0xxxxx firmware revision(8 ascii characters) 27- 46 0xxxxx 0xxxxx model number 47 0x8010 0x8010 number of sectors on multiple commands 48 0x0000 0x0000 reserved 49 0x2b00 0x2b00 capabilities 50 0x4000 0x4000 capabilities 51 - 52 0x0000 0x0000 obsolete 53 0x0007 0x0007 reserved 54 0x3fff 0x3fff number of current logical cylinders 55 0x0010 0x0010 number of current logical heads 56 0x003f 0x003f number of current logical sectors per track 57 0xfc10 0xfc10 current capacity in sectors 58 0x00fb 0x00fb 59 0x0110 0x0110 multiple sector setting 60 0x0000 0x0000 total number of user addressable sectors(lba mode only) 61 0x01e8 0x03d0 62 0x0000 0x0000 obsolete 63 0x0007 0x0007 multi-word dma transfer 64 0x0003 0x0003 flow control pio transfer modes supported 65 0x0078 0x0078 minimum multiword dm a transfer cycle time per word 66 0x0078 0x0078 manufacturer?s recommended multiword dma transfer cycle time per word 67 0x00f0 0x00f0 minimum pio transfer cycle time without flow control 68 0x0078 0x0078 minimum pio transfer cy cle time with iordy flow control 69 - 74 0x0000 0x0000 reserved 75 0x0000 0x0000 no dma queued command supports 76 - 79 0x0000 0x0000 reserved 80 0x003c 0x003c ata5 rev3 81 0x0013 0x0013 82 0x342b 0x342b command set supported 83 0x4101 0x4101 command set supported 84 0x4000 0x4000 command set/feature supported extension 85 0x3428 0x3428 command set/feature enabled 86 0x4101 0x4101 command set/feature enabled 87 0x4000 0x4000 command set/feature default 88 0x101f 0x101f ultra dma transfer 6.7 identify device data
nand flash-based solid state disk 60 sep. 27. 2006 word 16gb 32gb description 89 - 91 0x0000 0x0000 reserved 92 0xfffe 0xfffe master password revision code 93 0x2040 0x2040 hardware reset result 94 - 126 0x0000 0x0000 reserved 127 0x0000 0x0000 removable media status notification feature set support 128 0x0001 0x0001 security status 129 - 159 0x0000 0x0000 vendor specific 160 - 254 0x0000 0x0000 reserved 255 0x0000 0x0000 integrity word
nand flash-based solid state disk 61 sep. 27. 2006 6.8 hardware reset state diagram dhr0:reset- pdiag-=x, dasp-=x, bsy=1 reset-negated(t=0) dhr0:dhr1 reset-asserted xx:dhr0 t=1ms d0hr1:sample_dasp- pdiag-=r, dasp-=r, bsy-=1 sample dasp- d0hr1:d0hr1 dasp-asserted d0hr1:d0hr2 d0hr1:d0hr3 clear bit 7 d0hr2:sample_pdiag- pdiag-=r, dasp-=r, bsy=1 resemble pdiag- d0hr2:d0hr2 pdiag-asserted t=31ms d0hr2b:d0hr3 set bit 7 dhr1:release_bus pdiag-=r, dasp-=x, bsy=1 bus release & device 1 dhr1:d1hr0 bus release & device 0 dhr1:d0hr1 d1hr0:set_dasp- pdiag-=r, dasp-=r, bsy=1 dasp-asserted d1hr0:d1hr1 d1hr1:set_status pdiag-=r, dasp-=a, bsy=1 status set, passed diagnostic d1hr1:di2 bsy=0, pdiag-=a device_idle_ns status set, failed diagnostic d1hr1:di2 bsy=0, pdiag-=n device_idle_ns d0hr3:set_status pdiag-=r, dasp-=r, bsy=1 status set d0hr3:di1 bsy=0 device_idle_s d0hr0:dasp-_wait pdiag-=r, dasp-=r, bsy=1 d0hr0:d0hr1 t=500ms d0hr2a:d0hr3 clear bit 7 bsy drq rel serv c/d i/o intrq dmarq pdiag- dasp- v00000rrvv
nand flash-based solid state disk 62 sep. 27. 2006 6.9 software reset state diagram d0sr0:srst pdiag-=r, bsy=1 srst cleared to zero & no device 1 (t=0) srst set to one xx:d0sr0 t=1ms d0sr2:d0sr2 resemble pdiag- d0sr1:d0sr2 t=31ms d0sr3:set_status pdiag-=r, bsy=1 d0sr1:pdiag-_wait pdiag-=r, bsy=1 bsy drq rel serv c/d i/o intrq dmarq pdiag- dasp- v00000rrvr d0sr0:d0sr3 clear bit 7 srst cleared to zero & no device 1 (t=0) d0sr0:d0sr1 d1hr1:set_status pdiag-=r, bsy=1 pdiag-asserted d0sr2a:d0sr3 clear bit 7 d0sr2b:d0sr3 set bit 7 status set d0sr3:di1 bsy=0 device_idle_s device0 : software reset state diagram
nand flash-based solid state disk 63 sep. 27. 2006 srst = 1 xx:d1sr0 d1sr1:release_pdiag- pdiag-=x, bsy=1 bsy drq rel serv c/d i/o intrq dmarq pdiag- dasp- v00000rrvr status set, passed diagnostics d1sr2:di2 bsy=0, pdiag-=a device_idle_ns d1sr0:srst pdiag-=x, bsy=1 d1sr2:set_status pdiag-=r, bsy=1 srst = 0 d1sr0:d1sr1 pdiag-released d1sr1:d1sr2 status set, failed diagnostics d1sr2:di2 bsy=0, pdiag-=n device_idle_ns device 1 : software reset state diagram
nand flash-based solid state disk 64 sep. 27. 2006 mc x xxx xxxxxx - xxxxx 12345 8 11 1415161718 67 910 1213 1. module: m 2. card: c 3~4. flash density 4g : 4g 8d: 8g ddp aq : 16g qdp bo : 32g(16g qdp*2) 5. feature e : nssd 6~8. nssd density 04g : 4g byte 08g : 8g byte 16g : 16g byte 32g : 32g byte 9. nssd type 6 : nssd type1(56x48) q : nssd type2(54x71) 10. component generation m : 1st generation a : 2nd generation b : 3rd generation c : 4th generation d : 5th generation 11. flash package p : tsop1(lf) 12. pcb revision and production site p : none(sts) q : 1st rev.(sts) r : 2nd rev.(sts) 13. " - " 14. packing type m : module type 15. controller x : s4ld166x01(lqfp) w : s4ld166x01(fbga) 16. controller firmware revision a : none b : 1st rev . c : 2nd rev . d : 3rd rev . z : none(no cont.) 17 ~ 18. customer grade " customer list reference " 7. ordering information
nand flash-based solid state disk 65 sep. 27. 2006 m-die based part number density type remark mcaqe16g6mpp-mxa 16gb small MCBOE32GQMPQ-MWA 32gb slim 8. product line-up a-die based part number density type remark mc8de08g6app-mxa 08gb small mcaqe16g6app-mxa 16gb small mcboe32gqapq-mwa 32gb slim mc4ge04gqapr-mwa 4gb slim will be available end of 2006 year. r code(12th) means shared pcb. mc8de08gqapr-mwa 8gb slim mcaqe16gqapr-mwa 16gb slim mcboe32gqapr-mwa 32gb slim

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